Front End Electronics for High Counting Rate TRD
نویسندگان
چکیده
Fast Analog Signal Processor FASP-0.1 [1, 2] is a prototype ASIC designed at NIPNE for HCR-TRD having in mind the CBM experiment at FAIR. In this contribution we report on relevant measured parameters of ASIC analog channels and a FEE based on FASP, designed and built for in-beam tests of our HCR-TRD prototypes [3]. ASIC measured parameters [4, 5] Quiescent supply current (VD = 3.3V): 30mA ±1mA. Output baseline shift : with power supply (VD = 3.03.6V): < 0.07%; with detector leakage current (IL=± 50nA):<9μV/nA. Conversion gain G vs. Cdet (for FAST outputs): Integral nonliniarity (INL)(0-1V linear range):
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